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Cadence updates Virtuoso for the 20nm generation

Cadence Design Systems has built into its latest update for the Virtuoso custom-design environment a number of features designed to tackle the problems of working with the 20nm generation of processes,...

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Electrically aware Virtuoso aims to head off physical issues

Cadence Design Systems has rolled out a new version of Virtuoso that is intended to deal with the increasing number of physical-implementation issues that arise in the sub-28nm nodes. Virtuoso...

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Old problems on a new scale

“Spice has been an evegreen problem for my entire adult life. It’s endless with it’s problems and possibiltities,” venture capitalist Jim Hogan told Brian Fuller, host of Cadence Design Systems’...

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Samsung applies early prediction and color management to 10nm plans

Rapid virtual prototyping and a metal stack that’s more designer friendly are two of the ways in which Samsung aims to build up foundry market share for its 14nm and 10nm finFET processes. In a...

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Deliver RFIC reliability and performance through automation

RFICs are not different from most other parts of chip design in having moved toward greater system-on-chip level integration, and as they have simulation budgets have been pushed to the limit. A new...

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Pulsic goes freemium with analog-preview tool

Pulsic has decided to adopt the freemium approach popularised by internet companies with the launch of a tool that gives designers of analog and mixed-signal circuits a better idea of how they will be...

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Intel talks 4 at VLSI

Intel described the attributes of its upcoming next-generation finFET process at this year’s VLSI Circuits and Technology Symposium. Using the company’s reworked naming scheme, Intel 4 is the follow-on...

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Siemens pushes DRC to the left

Siemens Digital Industries Software has expanded its Calibre lineup for design-rule and manufacturability checks with a version of the engine that makes it easier to perform useful checks early in the...

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